1. Field of the Invention
The present invention relates to a latch circuit and, particularly, to a latch circuit for latching data at an edge of a clock signal.
2. Description of the Related Art
A latch circuit for latching input data at an edge of a control signal such as clock signal has been used popularly as a logic circuit in an integrated circuit or a semiconductor device. For example, FIG. 3 is a block circuit diagram showing a construction of a conventional latch circuit.
The conventional latch circuit comprises an inverter 51 for inverting a clock signal CLK and outputting an inverted clock signal iCLK, a master portion 52 and a slave portion 53. The master portion 52 and the slave portion 53 are connected in series between an input terminal and an output terminal for controlling a signal transmission between the input terminal and the output terminal correspondingly to the clock signal CLK and the inverted clock signal iCLK, respectively.
The master portion 52 is controlled by the clock signal CLK and the inverted clock signal iCLK. The master portion 52 includes an input transfer gate 521 controlled by the inverted clock signal iCLK for transferring an input signal, two-stage inverters 522 and 523 for amplifying the input signal thus transferred and a feedback transfer gate 524 controlled by the clock signal CLK for feeding an output of the inverter 523 back to an input thereof. The slave portion 53 has the same construction as that of the master portion 52 and includes an input transfer gate 531 controlled by the clock signal CLK for transferring an input signal, two-stage inverters 532 and 533 for amplifying the input signal thus transferred and a feedback transfer gate 534 controlled by the inverted clock signal iCLK for feeding an output of the inverter 533 back to an input thereof.
An operation of this conventional latch circuit will be described briefly. The master portion 52 takes in an input signal DIN in response to a low level of the clock signal CLK and outputs a signal held in the slave portion 53 as a latch output signal Q.
Then, when the clock signal CLK is changed to a high level, the input signal taken in by the master portion 52 is held therein and, simultaneously, the input signal is taken in by the slave portion 53 and outputted thereby as the latch output signal Q.
Therefore, the latch circuit latches the input signal DIN and outputs it as the output signal Q in synchronism with the change of the level of the clock signal CLK from low to high.
In order to guarantee the operation of the latch circuit, a setup time or a hold time is set as a speck value defining the timing of change of the input signal DIN. The setup time is a minimum time required for latching the input signal DIN before the change of the clock signal CLK and the hold time is a minimum time required for latching the input signal DIN after the change of the clock signal CLK.
In a case where a plurality of latch circuits are used, the timing of the change of clock signal and input signal in each latch circuit depends upon external conditions. Therefore, the setup time and the hold time set for each latch circuit by the clock signal as a reference varies and the setup time and the hold time of the whole latch circuits becomes the worst one of the speck values of the latch circuits.
The setup time or the hold time of an SDRAM or DDR-SDRAM which uses the conventional latch circuits is severely determined compared with that of a conventional DRAM, since the SDRAM or the DDR-SDRAM is operated at high speed. However, it becomes difficult to satisfy the setup time or the hold time required for the conventional latch circuit correspondingly to such high speed operation.
Describing the reason for this by taking the setup time, as an example, which is the minimum time for latching the input signal DIN changed in level before the level of the clock signal CLK is changed, the minimum time corresponds to a minimum propagation time from a time when the changed input signal DIN is propagated to the feedback transfer gate 524 of the master portion 52 to a time at which the input signal is determined as a hold data by a turning on of the feedback transfer gate 524 corresponding to the level change of the clock signal CLK. However, delay time of a latch circuit varies depending upon the kind of latch circuit, causing the design of the latch circuit to become difficult. This is also true for the hold time.